Evaluation of Fault Coverage as The Metric for Different Faults in VLSI Circuits using 2D-LFSR

P Basker, V Arun Kumar

Abstract


The test generation problem for VLSIcircuits is known to be NP-hard. Efficient techniques for test generation are essential in order to reduce the test generation time. Test patterns were generated using ATPG (Automatic Test Pattern Generation) and faults were inserted in the netlist file generated using DFT (Design for Test). Here ATPG is achieved using the combination of design compiler and the Tetramax. Fault coverage and test patterns were generated. It was observed that neither a comprehensive functional verification sequence nor a sequence with high stuck-at fault coverage gives high transition fault coverage for sequential circuits. A customized 2DLFSR algorithm is used to find the fault coverage and pattern used to detect the faults .


Keywords


DFT-ATPG-Struck at fault-Transition fault-Iddq fault-2D-LFSR.

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