Implementation of Parallel Multiplier 4x4 Low Power Design Using FPGA

M Prasanna Kumar, K Ashok Kumar

Abstract


In the fast growing communication field, requirements of low power designs are increasing to reduce the power losses and decrease the thermal losses in the same ratio. Multiplier is an arithmetic circuit that is extensively used in common DSP and Communication applications. This paper presents low power multiplier design methodology that inserts more number of zeros in the multiplicand thereby reducing the number of switching activities as well as power consumption. Modifying the structure of adders further reduces switching activity. The low power achievements can be done with help of Xilinx 7.1i the target device is Spartan 3 – xc3s400. In existing system such as 4 x 4 row bypassing architecture which needs the extra correction circuitry and structure of full adder is also complex. Another method such as Braun multiplier removes the extra correction circuitry but the limitation of this technique is that it cannot stop the switching activity even if the bit coefficient is zero that results in unnecessary power dissipation. In the proposed system the speed has been increased by using modified full adder and modified half adder. There is no unnecessary power dissipation.

Keywords


Low Power, Multiplier, Reduced Switching, Column By passing.

References


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