Low Power Design of Content-Addressable Memory using Xilinx FPGA

K Ashok kumar, M Thamarai selvan, V Sathish kumar

Abstract


Content-addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due to its ability to improve application performance by using parallel comparison to reduce search time. Although the use of parallel comparison results in reduced search time, it also significantly increases power consumption. In this paper, we propose a Block-XOR approach to improve the efficiency of low power precomputation-based CAM (PB-CAM). Through mathematical analysis, we found that our approach can effectively reduce the number of comparison operations by 50% on average as compared with the ones-count approach for 32-bit-long inputs. In our experiment, we used Synopsys Nanosim to estimate the power consumption in TSMC 0.35- m CMOS technology. Compared with the ones-count PB-CAM system, the experimental results show that our proposed approach can achieve on average 30% in power reduction and 32% in power performance reduction. The major contribution of this paper is that it presents theoretical and practical proofs to verify that our proposed Block-XOR PB-CAM system can achieve greater power reduction without the need for a special CAM cell design. This implies that our approach is more flexible and adaptive for general designs.

Keywords


CAM, Xor Block, Half Adder, Full Adder.

References


K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory (CAM) circuits and architectures:A tutorial and survey,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 712–727, Mar. 2006.

H. Miyatake, M. Tanaka, and Y. Mori, “A design for high-speed-low power CMOS fully parallel content-addressable memory macros,” IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 956–968, Jun. 2001. [3] I. Arsovski, T. Chandler, and A. Sheikholeslami, “A ternary contentaddressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 155–158, Jan. 2003.

I. Arsovski and A. Sheikholeslami, “A mismatch-dependent power allocation

technique for match-line sensing in content-addressable memories,”

IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1958–1966, Nov. 2003.

Y. J. Chang, S. J. Ruan, and F. Lai, “Design and analysis of low power cache using two-level filter scheme,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 4, pp. 568–580, Aug. 2003.

K. Vivekanandarajah, T. Srikanthan, and S. Bhattacharyya, “Dynamic filter cache for low power instruction memory hierarchy,” in Proc. Euromicro Symp. Digit. Syst. Des., Sep. 2004, pp. 607–610.

R. Min, W. B. Jone, and Y. Hu, “Location cache: A low-powre L2 cache system,” in Proc. Int. Symp. Low Power Electron. Des., Apr. 2004, pp. 120–125.

K. Pagiamtzis and A. Sheikholeslami,“Using cache to reduce power in content-addressable memories (CAMs),” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2005, pp. 369–372.

C. S. Lin, J. C. Chang, and B. D. Liu, “A low-power precomputationbased fully parallel content-addressable memory,” IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 622–654, Apr. 2003.

K. H. Cheng, C. H.Wei, and S. Y. Jiang, “Static divided word matching line for low-power content addressable memory design,” in Proc. IEEE Int. Symp. Circuits Syst., May 2004, vol. 2, pp. 23–26.

S. Hanzawa, T. Sakata, K. Kajigaya, R. Takemura, and T. Kawahara, “A large-scale and low-power CAMarchitecture featuring a one-hotspot block code for IP-address lookup in a network router,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 853–861, Apr. 2005.

Y. Oike, M. Ikeda, and K. Asada, “A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture,” IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1383–1387, Aug. 2004.

K. Pagiamtzis and A. Sheikholeslami, “A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme,”

IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1512–1519, Sep. 2004.

D. K. Bhavsar, “A built-in self-test method for write-only content addressable memories,” in Proc. 23rd IEEE VLSI Test Symp., 2005, pp. 9–14.


Full Text: PDF

Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.

.......................................................................................................................................................................................................................

ISSN  2279 – 0381 |  IST HOMEJOURNAL HOME | Copyright IST 2012-13

.......................................................................................................................................................................................................................