Design of Wallace Multiplier Using Gdi Based 10t Full Adder

A Harikishan, D Babukannan, D Somasundareswari

Abstract


An overview of the performance of various full adders in different CMOS logic styles and in depth the advantages and limitations of each of them with respect to delay, power dissipation and PDP is presented. Hybrid adders are chosen for the extensive evaluation and a new low power and high performance hybrid full adder is designed in 90nm Technology. The adder cell is categorized into three modules. The modules are two XOR gates designed using 4 transisters in Gate Diffusion Input (GDI) technique and third module is carry block designed using GDI mux. The proposed adder produce 52.7% decrease in PDP value than existing hybrid adder for supply voltage Vdd = 1.2V. Besides analyzing and comparing circuit performance, the possible impact of the choice of logic function has also been underlined in this study. DSCH and MICROWIND tool is used for the circuit design and Simulation respectively.


Keywords


Hybrid, PDP, low power, full adder & VLSI.

References


Vivek Kumar, Viranda Gupta and Rohit Maurya, July 2012,”A Study and Analysis Of High Speed Adders in Power-Constrained Environment”, International Journal of Soft Computing and Engineering, Vol-2. Issue-3,

Rajkumar Sarma and Veerati Raju, June 2012,” Design And Performance Analysis Of Hybrid Adders For High Speed Arithmetic Circuit”, International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3.

Mohammad Javad Zavarei, Mohammad Reza Baghbanmanesh, Ehsan Kargaran, Hooman Nabovati and Abbas Golmakani, 11-14 Dec 2011,” Design of New Full Adder Cell Using Hybrid- CMOS Logic Style”, Electronics ,circuits and systems (ICECS),2011 18th IEEE International Conference.

N.Weste and K. Eshraghian, 2011,Principles of CMOSVLSI Design, A System Perspective. Reading, MA: Addison-Wesley.

T. Vigneswaran, B. Mukundhan, and P. Subbarami Reddy, 13 2008,” A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem”, World Academy of Science, Engineering and Technology.

Keivan Navi. Omid Kavehie, Mohnoush Rouholamini, Amir Sahafi and Shima Mehrabi, 2007,” A Novel CMOS Full Adder”, International Conference on VLSI Design (VLSID).

Sumeer Goel, Ashok Kumar, and Magdy A. Bayoumi, December 2006, ” Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style”, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 12.

Massimo Alioto, and Gaetano Palumbo, December 2002, “Analysis and Comparison on Full Adder Block in chnology”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 6.

Ahmed M. Shams,Tarek K, Darwish, and Magdy A. Bayoumi, , February 2002, ” Performance Analysis of Low-Power 1-Bit CMOS Full Adder Cells”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 1.

D.A.Pucknell, K.Eshraghian, Basic VLSI Design--Prentice Hall, 1994 ISBN 0-13-079153-9.


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