An LFSR Seed Based Low Power Test Pattern Generator Using Enetic Algorithm

A Aishwarya, M Sri Saranya

Abstract


Integrated Circuit (IC)  testing, for its proper functioning is a time consuming and a demanding process. Incorporating the IC’s within complex systems have paved way for the rapid growth in the increase of cost for the testing. The   Most common behaviour to deal with the problem of testing at the chip level is to make use of built-in self-test (BIST). BIST reduces testing complexity and it is highly reliable. BIST   mainly involves in improving the controllability and the observability of the circuit, eventually leading to make ease of test generation and fault detection. In this paper the test patterns are generated by using Linear feedback shift register (LFSR).From the patterns of LFSR different initial seeds are taken and given as input patterns to Benchmark circuits. Test application time for different initial seeds of LFSR are detected and test time is reduced by providing best initial seed of LFSR. Genetic algorithm is applied for selecting best seed for LFSR that produces test vectors for the Circuit Under Test (CUT) yielding maximum fault coverage with reduced test application time. This work mainly ensures in maximum fault coverage with reducing testing time for a circuit.


Keywords


Built in Self Test (BIST), Linear feedback shift register (LFSR), Genetic algorithm (GA) ,LFSR Seed, Test application time, Circuit Under Test (CUT),Design for Testability(DFT), Integrated Circuits (IC).

References


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